1. Field of Invention
The present invention relates to a semiconductor device and a fabrication method thereof. More particularly, the present invention relates to a semiconductor device and a fabrication method thereof in which a device isolation layer is formed in a field region of a silicon on insulator (SOI) substrate for a field insulator field effect transistor (FinFET) device.
2. Description of Related Art
The application of nano-complementary metal-oxide-semiconductor (CMOS) device technology to memory devices, such as central processing units (CPUs), results in substantial added value. Nano-CMOS is relatively new technology and substantial research is being performed throughout the world as a result of the added value that may be obtained. A FinFET device is an example of a device produced using nano-CMOS technology.
Conventional techniques for fabricating FinFET devices are disclosed in Electron Devices Meeting (IEDM Technical Digest, International 2-5 December 2001, Pages 19.1.1-19.1.4) and Electron Device Letters (IEEE, Volume 24, Issue 3, March, 2003, Pages 186-188).
In the conventional FinFET manufacturing method, an elevated field insulator (LFIN) is used to form a device isolation layer in a field region of a silicon on insulator (SOI) substrate. An active region is formed in the SOI substrate through this process.
More particularly, a silicon substrate and an SOI substrate are first prepared. The SOI substrate includes a buried oxide layer and a silicon epitaxial layer. A gate oxide layer, a polycrystalline silicon layer, and a pad nitride layer are formed, in this sequence, on the SOI substrate. Next, using photolithography, the nitride layer is removed from the field region of the SOI substrate to thereby form a nitride layer pattern in the active region of the SOI substrate.
Following the above processes, the nitride layer pattern is used as a hard mask layer to perform etching of the polycrystalline silicon layer, the gate oxide layer, and the silicon epitaxial layer in areas outside of the nitride layer. A trench is formed through this process.
Next, gap filling using an insulation layer (e.g., an oxidation layer) is performed in the trench, after which the insulation layer is flattened through a process of chemical-mechanical polishing. Accordingly, a device isolation layer is formed in the field region of the SOI substrate to define an active region in the SOI substrate.
A drawback, however, of the above conventional method is as follows. As a result of the accumulation of the nitride layer on the polycrystalline silicon layer, flat vertical side surfaces of the nitride layer pattern are not achieved after forming the nitride layer pattern through photolithography. This is caused by diffused reflection occurring on the polycrystalline silicon layer during exposure to form a pattern of a photosensitive layer that corresponds to the pattern of the nitride layer.
If the nitride layer pattern formed with the above defect is used as an etching mask layer to perform dry etching (e.g., reactive ion etching) of the polycrystalline layer, the gate oxide layer, and the silicon epitaxial layer, striations may be formed in the silicon epitaxial layer. Other defects, such as facets, may also be generated in the silicon epitaxial layer.
FIG. 1 is a photograph taken by an electron microscope, and is used to observe etching surfaces of the silicon epitaxial layer, gate oxide layer, and the polycrystalline silicon layer. It is evident from the photograph that striations S are formed in the etched side surfaces.
Facets and striations may cause an increase in a leakage current of a junction formed in the active region of the SOI substrate, and may otherwise degenerate the characteristics of the transistor used for a FinFET device.